1. Field
The present application generally relates to a synchronization circuit and, more particularly, to a digital phase synchronization circuit for synchronizing clock signals and digital input signals.
2. The Related Art
Multiple integrated circuits often output signals that must be fed to a single integrated circuit. Signal skew can develop between the output signals from a variety of sources, including chip-chip variation and signal path differences. Further, clock skew on an integrated circuit can develop from the same sources. The signal and clock skew has been dealt with by equalizing signal path lengths and manually providing phase adjustment.
In addition, high speed systems designed with multiple integrated circuits rely on careful control of signal and clock traces to maintain phase alignment of multiple signals and clocks. Phase lock loops have been used in conjunction with first-in-first-out memories in high frequency applications to provide a clock interface between a clock recovered from the signal and the local clock on the integrated circuit. Such phase lock loops dissipate a lot of power, are only useful for a small number of inputs, for example, four inputs to a chip, and have a slow acquisition time.
What is needed is a digital phase synchronization circuit that uses a digitally controlled delay line in conjunction with at least one phase detector to change the delay in a signal path relative to a local clock. Also, there is a need for such a circuit that eliminates signal and clock skew with lower power dissipation and which can be used for a greater number of inputs.